1. Field of the Invention
This invention generally relates to error signal accumulation and, more particularly, to a system and method to perform a first order accumulation of an error signal in a single clock cycle.
2. Description of the Related Art
FIG. 1 is a schematic block diagram depicting an accumulator circuit capable of performing a division operation (prior art). As noted in “A Pipelined Noise Shaping Coder for Fractional-N Frequency Synthesis”, by Kozak et al., IEEE Trans. on Instrumentation and Measurement, Vol. 50, No. 5, October 2001, the depicted 4th order device can be used to determine a division ratio using an integer sequence.
The carry outs from the 4 accumulators are cascaded to accumulate the fractional number. The carry outs are combined to reduce quantization noise by adding their contributions are follows:contribution 1=c1[n]; contribution 2=c2[n]·c2[n−1];contribution 3=c3[n]·2c3[n−1]+c3[n−2];contribution 4=c4[n]·3c4[n−1]+3c4[n−2]−c4[n−3];
where n is equal to a current value, and (n−1) is the previous value.
FIG. 2 shows the contributions made by the accumulator depicted in FIG. 1 with respect to order (prior art). A fractional number is a number that expresses a ratio of a numerator divided by a denominator. Some fractional numbers are rational—meaning that the numerator and denominator are both integers. With an irrational number, either the numerator or denominator is not an integer (e.g., π). Some rational numbers cannot be resolved (e.g., 10/3), while other rational numbers may only be resolved using a large number of decimal (bit) places. In these cases, or if the fractional number is irrational, a long-term mean of the integer sequence must be used as an approximation.
The bottleneck in many controllers, such as a digital phase detector voltage controlled oscillator (VCO) controller used in a clock and data recovery (CDR) device, is the latency of feedback loop. Since the latency of the feedback loop determines the performance of CDR locking, tracking, and jitter, the feedback design must keep the latency as low as possible. The inherent latency of conventional digital circuitry limits the use of purely digital oscillator circuitry to relatively low frequencies.
Parent application, entitled FLEXIBLE ACCUMULATOR FOR RATIONAL DIVISION, Ser. No. 11/954,325, discloses an accumulator able to generate rational number quotients. However, as with conventional designs, the accumulated result is created over the course of several cook cycles.
It would be advantageous if an accumulator could minimize latency by creating a first order result in a single clock cycle.